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  february 2013 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller FCM8531 ? mcu embedded and configurable 3-phase pmsm / bldc motor controller features advanced motor controller (amc) ? configurable processing core - sensorless field-oriented control (foc) with speed integral method - sensorless foc with sliding mode - hall interface ? space vector modulation (svm) ? sine-wave & square-wave generator ? programmable current leading phase control ? programmable soft-switching control (dead time) embedded mcu ? mcs ? 51 compatible ? 63% of instructions? execution cycle <3 system clocks (3t) ? memory size: - 12 kb flash program memory - 256 +1 kb sram data memory ? extended16-bit multiplication / division unit (mdu) ? 17 general-purpose input / output (gpio) pins ? full duplex serial interface (uart) ? i 2 c interface ? serial peripheral interface (spi) ? three external interrupts ? three 16-bit timers ? programmable 15-bit watchdog timer (wdt) ? built-in power-on reset (por) ? built-in clock generator ? two-level program memory lock adc and dac ? 8-channel, 10-bit adc - auto-trigger sample & hold - four trigger mode selections - three pre-amp gain selections ? 1-channel, 8-bit dac protections ? three levels of over-current protection (ocp) power management ? idle mode, stop mode, sleep mode development supports ? in system programming (isp) ? on-chip debug support (ocds) description the FCM8531 is an applicati on-specific parallel-core processor for motor control that consists of an advanced motor controller (amc) processor and a mcs ? 51-compatible mcu processor. the amc is the core processor specifically designed for motor control. it integrates a configurable processing core and peripheral circuits to perform foc and ?sensorless? motor control. system control, user interface, communication interface, and input/output interface can be programmed through the embedded mcs ? 51 for different motor applications. the advantage of FCM8531?s parallel-core processors is that the two processors can work independently and complement each other. the amc processes the tasks dedicated for motor controls, such as the motor control algorithms, pwm controls, current sensing, real-time over-current protection, and motor angle calculation. the embedded mcu provides motor control commands to the amc to perform motor control activities through a communication interface. this approach reduces the software burden and simplifies the control system program because complex motor control algorithms are executed in the amc. fairchild provides the motor control development system (mcds) ide and mcds programming kit for users to develop software, compile programs, and perform online debugging. applications ? sensorless ipm / spm, bldc / pmsm motor ? fan, blower, pump, power-tool, e-bike, compressor, etc. related resources ? an-8202 FCM8531 user manual - hardware description ? an-8203 FCM8531 user manual - instruction set ? user guide for FCM8531 evaluation board ordering information part number operating temperature range package packing method FCM8531qy -40 o c to 85 o c 32-lead, lqfp, jedec ms-026, variation bba, 7 mm square tray
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 2 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller application diagram figure 1. typical application circuit
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 3 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller f - fairchild logo z- plant code x-1-digit year code y- 1-digit week code tt: 2-digit die run code t:package type (q=lqfp) p: y=green package m: die run code block diagram port gpio 0 gpio 1 gpio 2 i/o peripheral figure 2. block diagram marking information 16 9 8 17 32 25 24 f zxytt FCM8531 tpm 1 figure 3. top mark
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 4 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller pin configuration figure 4. pin configuration pin definitions pin # name type description 1 p10 i/o bit 0 of port 1 . general-purpose input/output pin with internal pull-up resistor. rx i data receive (uart) scl i/o serial clock (i 2 c) spssn i/o spi slave select (spi) 2 p11 i/o bit 1 of port 1 . general-purpose input/output pin with internal pull-up resistor. tx o serial data transmit (uart) sda i/o serial data (i 2 c) mosi i/o master data output and slave data input (spi) 3 p12 i/o bit 2 of port 1 . general-purpose input/output pin with internal pull-up resistor. scl i/o serial clock (i 2 c) rx i data receive (uart) miso i/o master data input and slave data output (spi) isp_scl i isp serial clock . serial clock input in isp mode. 4 p13 i/o bit 3 of port 1 . general-purpose input/output pin with internal pull-up resistor. sda i/o serial data (i 2 c) tx o serial data transmit (uart) sck i/o serial clock (spi) isp_sda i/o isp serial data . serial data input/output pin in isp mode. 5 p14 i/o bit 4 of port 1 . general-purpose input/output pin with internal pull-up resistor. spssn i/o spi slave select (spi) rx i data receive (uart) scl i/o serial clock (i 2 c) tdo o test data output . test data output in ocds mode. continued on the following page?
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 5 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller pin definitions (continued) pin # name type description 6 p15 i/o bit 5 of port 1 . general-purpose input/output pin with internal pull-up resistor. mosi i/o master data output and slave data input (spi) tx o serial data transmit (uart) sda i/o serial data (i 2 c) tdi i test data input . test data input in ocds mode. 7 p16 i/o bit 6 of port 1 . general-purpose input/output pin with internal pull-up resistor. miso i/o master data input and slave data output (spi) scl i/o serial clock (i 2 c) rx i data receive (uart) tms i test mode select . test mode select in ocds mode. 8 p17 i/o bit 7 of port 1 . general-purpose input/output pin with internal pull-up resistor. sck i/o serial clock (spi) sda i/o serial data (i 2 c) tx o serial data transmit (uart) tck i test clock . test clock input in ocds mode. 9 p24 i/o bit 4 of port 2 . general-purpose input/output pin with internal pull-up resistor. cc0 i/o timer2 compare/capture channel 0 t0 i timer0 external input t2 i timer2 external input 10 p25 i/o bit 5 of port 2 . general-purpose input/output pin with internal pull-up resistor. cc1 i/o timer2 compare/capture channel 1 t1 i timer1 external input t2ex i timer2 external trigger 11 p26 i/o bit 6 of port 2 . general-purpose input/output pin with internal pull-up resistor. cc2 i/o timer2 compare/capture channel 2 t2 i timer2 external input t0 i timer0 external input 12 rst i system reset . hardware reset i nput, active high. 13 vc ai analog input . 10-bit adc input (middle sampling rate). the adc result stores in vcl and vch registers (2ch, 2dh) of msfr. 14 vb ai analog input . 10-bit adc input (middle sampling rate). the adc result stores in vbl and vbh registers (2ah, 2bh) of msfr. 15 va ai analog input . 10-bit adc input (middle sampling rate). the adc result stores in val and vah registers (28h, 29h) of msfr. 16 adc3 ai analog input . 10-bit adc input (low sampling rate).the adc result stores in adc3l and adc3h registers (36h, 37h) of msfr. aout ao analog output . 8-bit dac output set by dac3 register (47h) of msfr. 17 avss p analog ground 18 adc0 ai analog input . 10-bit adc input (low sampling rate). the adc result stores in adc0l and adc0h registers (30h, 31h) of msfr. 19 ic ai phase c current input . 10-bit adc input (high sampling rate). the adc result stores in icl and ich registers (24h, 25h) of msfr. continued on the following page?
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 6 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller pin definitions (continued) pin # name type description 20 ib ai phase b current input . 10-bit adc input (high sampling rate). the adc result stores in ibl and ibh registers (22h, 23h) of msfr. 21 ia ai phase a current input . 10-bit adc input (high sampling rate). the adc result stores in ial and iah registers (20h, 21h) of msfr. 22 avdd p 5.0 v analog voltage input . a 0.1 f (minimum) capacitor should be connected between this pin and avss. 23 dvdd p 5.0 v digital voltage input . a 0.1 f (minimum) capacitor should be connected between this pin and dvss. 24 v25 o 2.5 v voltage regulator output . a 0.1 f (minimum) capacitor should be connected between this pin and dvss. 25 dvss p digital ground 26 vpp p programming supply voltage . v pp = 12 v for flash memory programming. 27 u o pwm output . high-side gate control signal of phase a. p02 i/o bit 2 of port 0 . general-purpose input/output pin with internal pull-down resistor. 28 x o pwm output . low-side gate control signal of phase a. p03 i/o bit 3 of port 0 . general-purpose input/output pin with internal pull-down resistor. 29 v o pwm output . high-side gate control signal of phase b. p04 i/o bit 4 of port 0 . general-purpose input/output pin with internal pull-down resistor. 30 y o pwm output . low-side gate control signal of phase b. p05 i/o bit 5 of port 0 . general-purpose input/output pin with internal pull-down resistor. 31 w o pwm output . high-side gate control signal of phase c. p06 i/o bit 6 of port 0 . general-purpose input/output pin with internal pull-down resistor. 32 z o pwm output . low-side gate control signal of phase c. p07 i/o bit 7 of port 0 . general-purpose input/output pin with internal pull-down resistor. notes: 1. type p: power pin. 2. type i: digital input pin. 3. type o: digital output pin. 4. type i/o: bidirectional input/output pin. 5. type ai: analog input pin. 6. type ao: analog output pin.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 7 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v pp programming supply voltage -0.7 13 v v dd supply voltage -0.7 7 v v vih voltage of i/o pin and rst pin with respect to gnd -0.2 v dd +0.2 v v an analog input voltage -0.2 v dd +0.2 v ? ja thermal resistance (junction-to-air) 80 ? c/w t a operating ambient tem perature range -40 85 ? c t stg storage temperature range -65 150 ? c esd electrostatic discharge capability human body model, jesd22-a114 3,000 v charged device model, jesd22-c101 1,250 recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v pp programming supply voltage 11.8 12.0 12.2 v
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 8 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller electrical characteristics v dd =5 v, and t a =25 ? c unless otherwise noted. symbol parameter conditions min. typ. max. unit f sys system frequency 29.4 30.0 30.6 mhz f sys system frequency at -40 ? c 28.5 31.5 mhz power management v dd_on turn-on voltage 4.5 v v dd _ off turn-off voltage 3.2 v v out v25 output voltage range load cu rrent < 10 ma 2.35 2.5 2.65 v i dd_oper v dd current at operation mode 20k hz pwm output 20 29 35 ma i dd_sleep (7) v dd current at sleep mode wake-up period = 37 ms 500 a t sleep (7) sleep mode period initial setting 40 ms flash memory (7) v pp program/erase supply vo ltage 11.8 12.0 12.2 v i vpp mass program current 8 ma t write page write time 1.55 ms t erase erase time 500 600 ms endurance erase + write 1000 cycle data retention 100 year 10-bit adc (7) r i input impedance 3 m ? v i_min minimum conversion voltage code 000h 0 v v i_max maximum conversion voltage code 3ffh 4 v dnl differential nonlinearity 2.0 lsb inl integral nonlinearity 2.0 lsb err adc offset error 3.0 lsb 8-bit dac (7) r o output impedance w/i, w/o current bias 10 k ? v o_min minimum conversion voltage code 00h 50 mv v o_max maximum conversion voltage code ffh 4 v dnl differential nonlinearity 1.0 lsb inl integral nonlinearity 2.0 lsb current limit v ocl_offset ocl comparator offset ocl = 10h -50 50 mv v och_offset och comparator offset och = c0h -50 50 mv v short_offset short comparator offset short = c0h -50 50 mv v ocl_rng (7) ocl comparator operation range 0 3.5 v v och_rng (7) och comparator operation range 1 4 v v short_rng (7) short comparator operation range 1 4 v i bias current source of ia/ib/ic 47.5 50.0 52.5 a i bias (7) current source of ia/ib/ic at -40 ? c 46 51 a continued on the following page?
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 9 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller electrical characteristics v dd =5 v, and t a =25 ? c unless otherwise noted. symbol parameter conditions min. typ. max. unit gpio v ih input high voltage 3.3 v v il input low voltage 1.8 v r up (7) p1, p2 pull-up resistor 40 k ? r down (7) p0, rst pull-down resistor 45 k ? i ol low level output current v ol = 0.4 v 2.3 ma i oh high level output current v oh = 0.8 x v dd 2.5 ma spi (7,9) t r(sck) spi clock rising time master mode, c l = 20 pf 60 ns t f(sck) spi clock falling time master mode, c l = 20 pf 60 ns t sck spi clock cycle time t sys x 8 ns t ens ssn setup time t sys x 3 ns t hs ssn hold time slave mode t sys x 3 ns t ds data input setup time master mode t sys ns slave mode t sys ns t dh(mo) data output hold time master mode t sys ns t dh(so) data output hold time slave mode t sys ns t dh(mi) data input hold time master mode t sys ns t dh(si) data input hold time slave mode t sys ns t dis(so) data output disable time slave mode t sys x 3 ns i 2 c interface (7,10) t scl i 2 c clock cycle time t sys x 120 ns t start i 2 c start bit setup time t scl / 2 ns t stop i 2 c stop bit setup time t scl / 2 ns t setup i 2 c data setup time t sys ns t hold i 2 c data hold time t sys ns notes: 7. these parameters are not tested in manufacturing. 8. t sys = 1 / f sys = 33.33 ns. 9. spi timing diagrams as figure 5 and figure 6. 10. i 2 c timing diagram as figure 7.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 10 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller timing diagrams figure 5. spi timing diagram? slave mode figure 6. spi timing diagram ? master mode figure 7. i 2 c interface timing diagram
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 11 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller typical performance characteristics figure 8. system frequency (f sys ) vs. temperature figure 9. v25 output voltage (v out ) vs. temperature figure 10. v dd operation current (i dd_opper ) vs. temperature figure 11. current source of ia/ib/ic (i bias ) vs. temperature 10ma 0ma
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 12 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller functional description advanced motor controller (amc) the amc is used for motor driving. it consists of several motor control modules; such as configurable processing core, pwm engine, and angle predictor. depending on the application, the configur able processing core can be configured with suitable amc library to perform different motor control algorithms, such as field-oriented control (foc) or sensorless control. for example, if the sensor less library is used as the control algorithm, the conf igurable processing core obtains the motor current via the internal adc to estimate the rotor angle. after that, a pwm engine is used to provide the pwm output drive signal to set the correct rotor angle. if the configurable processing core is configured with the hall interface library, the rotor position information is input by gpio and the rotor angle is estimated using the angle predictor. the pwm engine can provide the appropriate pwm output drive signals for motor driving. configurable processing core the amc can be configured with different libraries, depending on the applicati on, via the motor control development system (mcds) integrated development environment (ide). for example: speed integral, sliding mode, or hall interface libraries can be activated. speed integral : this is a sensorless foc library where d-axis phase error is compensated by a large integrator to achieve more stable speed response. fewer parameters are required to set with speed integral. applications with static l oad, such as fans, can adopt this library. figure 12. speed integral block diagram sliding mode : this is a sensorless foc library with more parameters to adjust and set. applications with dynamic loads; such as water pumps, oil pumps, and compressors; can adopt this library. figure 13. sliding mode block diagram hall interface: this library is used in hall sensor motor control systems with square / sinusoidal wave drive. for more information, please see: amc library user guide - speed integral for FCM8531 amc library user guide - sliding mode for FCM8531 amc library user guide - hall interface for FCM8531 pwm engine the pwm engine includes four circuit modules: saw generator, square-wave pwm generator, sine-wave pwm generator, and pwm mux. figure 14. pwm engine block diagram the saw generator determines the pwm waveform and carrier frequency. there are three modes of carrier waveforms; up, down, and up-down; set using the sawmod bit in the sawcntl register in msfr (motor special function registers) ( see figure 15 ). figure 15. saw output mode
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 13 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller the pwm carrier frequency is decided by the prescal and the posscal in the sprdh/l and sawcntl registers in msfr. the pwm frequency, when saw is in the up-down mode, can be obtained using the following formula: f : : / : (1) the pwm frequency formula for saw in the up and down modes is calculated by: f : : / : (2) please refer to an-8202?FCM8531 user manual - hardware description for details. saw generator the square-wave pwm generator generates square- wave pwm signals with a default pattern based on a built-in table of default square-waves ( see table 1 ). corresponding pwm output signals are determined by the pattern of hall input signals or the hall register, while direction is determined by the cw setting. in addition to generating default square-wave pwm output waveforms, a custom izable user-defined square- wave table is also provided. this enables users to define special square-wave output waveforms according to application requirements. table 1. default square-wave table cw hall hall u-v-w x-y-z x 0 0 0 0 0 0 0 0 0 0 x 1 1 1 7 0 0 0 0 0 0 1 0 0 1 1 p 0 0 pb 1 0 1 0 1 1 3 0 0 p 0 1 pb 1 0 1 0 2 0 0 p 1 0 pb 1 1 1 0 6 0 p 0 1 pb 0 1 1 0 0 4 0 p 0 0 pb 1 1 1 0 1 5 p 0 0 pb 0 1 0 1 0 1 5 0 0 p 1 0 pb 0 1 0 0 4 0 0 p 0 1 pb 0 1 1 0 6 p 0 0 pb 1 0 0 0 1 0 2 p 0 0 pb 0 1 0 0 1 1 3 0 p 0 0 pb 1 0 0 0 1 1 0 p 0 1 pb 0 notes: 11. x: don?t care. 12. p: pwm. 13. pb: pwm inverse. in square-wave mode, the pwm duty is determined by the dutya and dutyal registers in msfr, with a total of 11 bits ( see figure 16 ). figure 16. pwm output the sine-wave pwm generator includes a space vector modulation (svm) circuit responsible for generating sine-wave pwm output waveforms. in addition to built-in sinusoidal waveform modulation, which is popular in many applications, a table allows users to customize pwm output waveforms. in sine-wave mode, the pwm duty is determined by the dutya register in msfr. when using the hall interface library, the pwm engine starts the motor in square-wave mode. after the angle predictor can accurately predict angles, the pwm engine automatically shifts to sine- wave mode. as shown in figure 17 (cw=0) and figure 18 (cw=1), corresponding pwm signals are generated based on the angle estimated from hall input signals. figure 17. default sine-wave pwm output (cw=0)
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 14 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller figure 18. default sine-wave pwm output (cw=1) angle predictor when using hall sensors for sine-wave control, the hall signals are used to accurately predict the rotor position of the motor. this information is provided to the svm circuit to calculate the space vector. two circuits are included in the angle predict or: hall signal filter and leading-angle shifter. the hall signal filter is responsible for hall signal debounce, blanking, regulation, and inversion. the rotor position can be adjusted using the leading- angle shifter. this can compensate for the current lag caused by motor winding inductance and further improve the motor efficiency. embedded mcu system flow control, user interface, input/output, and communication interface can be programmed and set in the embedded mcu. the instruction set is fully compatible with mcs ? 51; therefore, a standard 805x assembler and compiler can be used for development. since FCM8531 uses advanced instruction architecture that only needs one system cl ock per instruction set, its computation speed is greatly improved compared with the conventional 8051 mcu, which needs 12 system clocks per instruction set. in addition to the normal 8051 mcu functions; such as gpio, timer0/1/2, isr, and uart; other communication interfaces; such as spi, i 2 c, and watchdog timer (wdt) functions; are also integrated into the embedded mcu. figure 19. embedded mcu block diagram memory map the 12kb flash program memory is divided into two parts. in the first section of the memory area, addresses 0000h~2effh, are used to store programs. addresses higher than 2effh are in the special area, including two groups of user-definable wave tables and one lock byte. when 0 is written into the highest bit of the lock byte, the ocds function is disabl ed. when 0 is written into any other bit, the flash memory is encrypted to secure the program code. flash memory must first be erased and then re-written. figure 20. program memory map four groups of register banks are provided in the 256- byte internal sram data memory. the first 128 bytes (00h~7fh) of the internal data memory can be read by immediate addressing or indirect addressing. the latter 128 bytes (80h~ffh) in the memory are overlapped with sfr. accessing data in sram must use indirect addressing, while sfr uses immediate addressing to read and write.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 15 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller the 1024 bytes of external sram data memory are addressed by a 16-bit dptr and use an movx instruction for accessing. figure 21. data memory map multiplication-division unit (mdu) the mdu, used for parallel calculations, can process 32-bit division, 16-bit multiplication, and 32-bit displacement and normalization calculations. after setting the calculation model, the mdu begins to execute calculation. meanwhile, mcu are freed to continue the subsequent flow without pausing. after calculation is completed, t he result is stored in sfr. figure 22. mdu mode gpio (general-purpose input / output) the FCM8531 has three gpio ports: p0[7:2], p1[7:0], and p2[6:4]. the output can be set to direct drive or open drain through dir0, dir1, and dir2 of the sfr. inside the FCM8531, p0[7:2] is pulled down to gnd by internal resistors and other digital ios are pulled up to 5 v with internal resistors. figure 23. gpio driver & buffer p0[7:2] can be defined as a gpio or pwm output signal (u, v, w, x, y, and z) by using p0_cfg of the sfr. after reset, p0[7:2] is pre-set to a pwm output signal and the other dio pins are pre-set as gpio ( see table 2 ). the multi-function pins p1[7:0] and p2[6:4] can be set through io_cfg (f9h) of the sfr ( see table 3 and table 4). table 2. port 0 function configuration p0_cfg 0 (default) 1 bit 7 pwm z channel p07 bit 6 pwm w channel p06 bit 5 pwm y channel p05 bit 4 pwm v channel p04 bit 3 pwm x channel p03 bit 2 pwm u channel p02 table 3. port 1 function configuration pin io_cfg[1:0] 00 (default) 01 10 11 p10 rx scl spssn spssn p11 tx sda mosi mosi p12 scl rx miso miso p13 sda tx sck sck p14 spssn spssn rx scl p15 mosi miso tx sda p16 miso miso scl rx p17 sck sck sda tx table 4. port 2 function configuration pin io_cfg[3:2] 00 (default) 01 10 11 p24 cc0 cc0 t0 t2 p25 cc1 cc1 t1 t2ex p26 cc2 cc2 t2 t0 interrupt the FCM8531 provides 16 interrupt sources (see table 5) that can be divided into five priority groups and four priority levels. most of the interrupt setti ngs are identical to the standard mcs51, except for the following: ? the external interrupt 0 input source pin can be assigned to p24 or p26 through io_cfg of the sfr (special function registers). the interrupt trigger mode can be set to low-level trigger and falling-edge trigger. ? external interrupt 1 is input via p25. the interrupt trigger mode can be set to low-level trigger and falling-edge trigger. ? the external interrupt 12 input signal can be assigned to p1[6:0]. when an interrupt occurs, int12_sta can be used to inspect which pin has been triggered. the interrupt trigger mode can be set to low-level trigger and falling-edge trigger. ? the other interrupt sources include: v dd low-voltage warnings, adc transformation completion trigger, hall signal trigger, slow hall signal, hall signal error, and short-circuit sensing. these can be used for developing the motor control system.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 16 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller ? when an interrupt occurs, the interrupt service executes interrupt service programs at the specified interrupt vector addresses. during an interrupt, another interrupt is only permitted if an interrupt source with a higher priority level occurs. table 5. interrupt vector interrupt source interrupt vector symbol trigger external interrupt 0 0003h ex0 fall, low timer 0 overflow 000bh et0 external interrupt 1 0013h ex1 fall, low timer 1 overflow 001bh et1 serial 0023h es0 timer2 002bh et2 i 2 c 0043h ex7 spi 004bh ex2 com0 0053h ex3 rise, fall com1 005bh ex4 rise com2 0063h ex5 rise fault 008bh ex8 adc ready trigger 0093h ex9 hall edge 009bh ex10 rise, fall, rise & fall amc 00a3h ex11 rise external interrupt 12 00abh ex12 rise, fall, rise & fall watchdog timer (wdt) the watchdog timer is a 15-bit counter that increases every 384 or 6144 system cycles. if there are software or hardware abnormalities, it resets automatically. when the watchdog timer is set in wdtrel of the sfr, it begins to count when the swdt bit of sfr ien1 is set to 1. when it counts to 7ffch and a timeout occurs, it internally resets. the watchdog timer must be refreshed before timeout. if unexpected errors occur, the watchdog timer is not refreshed. after timeout, the program restarts. motor special function registers (msfrs) msfrs are registers used exclusively for motor control modules. they are accessed through mcu sfrs. parameters such as motor control, hall signal configure, waveform type, pwm engine, and over-current protection level can be set in msfrs. the adc and controller status (e.g., fault status, hall status, and pwm status) can be obtained via msfrs. adc and dac the analog signal input pins (ia, ib, ic, va, vb, vc, adc0, and adc3/aout) can be programmed for current sensing, voltage feed back, speed control, over- temperature protection, or other analog signal inputs; depending on the application. the adc3/aout pin location can be used as 0~4 v analog output. the output voltage is set via the dac in the msfr. the internal adc is divided into three groups according to the speed of the sampling rate ( see table 6 ). table 6. adc sampling rate sampling rate speed channel convert period high ia, ib, ic 1 adc trigger mid va, vb, vc 4 adc trigger low adc0, adc3 16 adc trigger pins ia, ib, and ic are preset as current-sensing input. when adc trigger signals occur, the sample-and-hold circuits retrieve the voltage to be converted. then it goes through a pre-amplifier to a 10-bit a-d converter. after conversion, it is stored in msfr and generates an adc-ready interrupt. adc trigger mode has four sub-modes: saw peak, saw valley, timer0, and manual trigger. figure 24. adc trigger mode protections protection functions are provided for hall signal error protection and over-current (cycle-by-cycle) protection. when a hall signal error occurs, the pwm pulse is turned off until the error status is released. cycle-by-cycle over-current protection (ocp) monitors every pwm cycle. if over-current is detected, the pwm is turned off until the next cycle. in addition to the cycle-by-cycle ocp, other protections generate interrupts. table 7. fault and protection type condition action hall slow hall period overflow interrupt 8 short a ia > i short interrupt 8 short b ib > i short interrupt 8 short c ic > i short interrupt 8 hall error hall sensor = 111 or 000 interrupt 8 pwm off oc high ia / ib / ic > i och pwm off oc low ia / ib / ic < i ocl pwm off
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 17 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller current protections there are three methods of current protection: negative over current, positive over current, and short-circuit sensing. the protection poin ts can be set via the ocl, och, and short of msfr. after a protection is triggered, pwm is immediatel y turned off until the next cycle (cycle-by-cycle). when the input voltage is higher than the short voltage, an ex8 interrupt is generated. corresponding measures can be executed to protect system based on requirements of application systems. figure 25. current protection (square-wave) each current-sensing pin (ia, ib, and ic) has an output of 50 a of bias current. the recommended setting for the bias voltage is 2.0 v (r bias = 40 k ? ). v bias = i bias x r bias (3) figure 26. current feedback circuit power management if v dd is > vdd on , the reset status takes about 2 ms to be released. FCM8531 provides three kinds of power-saving modes: ? in idle mode; execution of mcu programs pauses, but the peripheral i/o circuits continue to work (e.g. pwm, external interrupt, timi ng, serial output, etc.). ? in stop mode; execution of programs, digital i/o interfaces, and all digital circuits pause. this mode continues until the occurrence of an ex0/ex1 external interrupt or a system reset. ? in sleep mode, the mcu and amc are both turned off. at this moment, the alarm timer begins to count. after a timeout, the mcu and amc are turned on again. development supports fairchild provides the motor control development system (mcds) integrated development environment (ide). on microsoft ? windows platforms, functions such as project building, program code generation, compilation , in-system programming (isp), and on- chip debug support (ocds) are supported. this facilitates software development and debugging. for detailed information please see: user guide for mcds ide of FCM8531.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 18 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller table 8. sfrs (special function registers) map hex x000 x001 x010 x011 x100 x101 x110 x111 hex f8 p0_cfg io_cfg int12_cfg int12_sta dir0 dir1 dir2 ff f0 b srst f7 e8 md0 md1 md2 md 3 md4 md5 arcon ef e0 acc spsta spcon spdat spssn e7 d8 adcon i2cdat i2cadr i2ccon i2csta df d0 psw d7 c8 t2con crcl crch tl2 th2 cf c0 ircon ccen ccl1 cch1 ccl2 cch2 c7 b8 ien1 ip1 srelh ircon2 bf b0 mtx0 mtx1 mtx2 mtx3 mrx0 mrx1 mrx2 mrx3 b7 a8 ien0 ip0 srell af a0 p2 a7 98 scon sbuf ien2 9f 90 p1 dps dpc msfradr msfrdat 97 88 tcon tmod tl0 tl1 th0 th1 ckcon 8f 80 p0 sp dpl dph dpl1 dph1 wdtrel pcon 87 table 9. msfrs (motor special function registers) map hex x000 x001 x010 x011 x100 x101 x110 x111 hex 78 7f 70 78 68 6f 60 67 58 5f 50 57 48 4f 40 mbusctl pt01 pt23 sleep och ocl short daco 47 38 reserved reserved reserved reserv ed reserved reserved angle mstat 3f 30 adc0l adc0h adc3l adc3h 37 28 val vah vbl vbh vcl vch adcinx bak 2f 20 ial iah ibl ibh icl ich occntl ocsta 27 18 halmxu halflt halsta hali nt hperl hperm hperh adccfg 1f 10 reserved reserved reserved rese rved reserved reserved reserved 17 08 pwmcfg sawcntl sprdl sprdh sdl ybl sdlybh sdlycl sdlych 0f 00 mcntl angctl as angdet dutyal dutya dutyb dutyc 07
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 19 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller physical dimensions figure 27. 32-low-profile, quad, flat pack package (lqfp) package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . a) conforms to jedec ms-026 variation bba b) all dimensions in millimeters. c) dimensioning and tolerancing per asme y14.5m-1994. e) dimensions are exclusive of burrs, mold flash, and tie bar protrusions. f) landpattern standard: qfp80p900x900x160-32bm. g) drawing file name: mkt-vbe32arev2 notes: 1.0 0.75 0.45 0.20 min 0.25 gage plane 0.15 0.05 7.1 6.9 1.6 max r0.08 min 12 top & bottom 1.45 1.35 see detail a detail a side view top view pin #1 ident 9.0 1 8 9 16 17 24 25 32 land pattern recommendation 8.70 8.70 0.45 1.80 0.80 7.0 d c seating plane 0.10 c b a 9.0 7.0 0.45 0.30 0.20 ca-bd 0.8 32x 32x 0.20 ca-bd all leadtips r0.08-0.20
? 2012 fairchild semiconductor corporation www.fairchildsemi.com FCM8531 ? rev. 1.0.1 20 FCM8531 ? mcu embedded and configurab le 3-phase pmsm/bldc motor controller


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